The present invention relates to circuits that can be used for interpolating between two discrete phase signals, for example from a voltage controlled oscillator (VCO).
Clock recovery circuits (CRC) are typically employed in the telecommunications industry to extract clock information from serially transmitted data streams. FIG. 1 follows a description in a book entitled, xe2x80x9cPhase-Locked Loops: Design, Simulation and Applicationsxe2x80x9d, p. 2, by Roland Best. In FIG. 1, a typical CRC 18 includes a phase detector 12, a loop filter 14, and a VCO 16. The phase detector 12 detects the phase difference between an incoming reference data stream 10 and that of an output signal 20 from the VCO 16 and issues adjustment signal 22 for the VCO 16. Once the adjustment signal 22 has been filtered through the loop filter 14, it feeds into the VCO 16 to modify its output 20 in a way such as to minimize the phase difference between its output 20 and that of the reference data stream 10.
One of the factors that influences how well the synthesized frequency 20 approximates the actual clock frequency in the incoming reference data stream 10 is the phase resolution of the VCO 16, which is typically determined by the number of delay stages inside the VCO. These delay stages are sometimes implemented by connecting a series of delay elements together to form a ring oscillator. For example, in FIG. 2, a two-stage ring oscillator of the prior art having four output phases is illustrated. The delay elements 24 in the two-stage ring oscillator 22 are designed in a way such that the phase of a signal 23 is delayed by 90 degrees every time the signal 23 goes through one of the delay elements 24. Since each delay element 24 also produces a complementary signal 25 that is 180 degrees out of phase with its main signal 23, a ring oscillator 22 with two delay elements 24 will produce four output phases. In order to attain a higher phase resolution, one can increase the number of delay elements 24 in the ring oscillator 22. For instance, adding three delay elements 24 to the above mentioned ring oscillator 22 would generate six additional phases for output selection.
However, as the speed of data transmission increases, the demand for shorter delay time heightens. For example, to generate a clock frequency of 1.5625 GHz with 64-phase element resolution, a ring oscillator would need to have 32 delay elements with each delay element having a propagation delay of only 20 picoseconds (ps). Moreover, the 64 outputs from the ring oscillator would have to be routed to a multiplexer, which would then have to switch between these outputs without adversely affecting the clock frequency. In addition, the 20 ps time resolutions have to be preserved throughout the routing of the output lines and the multiplexing. These high-speed requirements would require a large amount of power dissipation and are quite incompatible with most current commercial semiconductor processes. As a result, for high-speed data transmission, phase interpolators that can interpolate between discrete clock phases, and thus increase the resolution of the CRC, are used.
U.S. Pat. No. 6,122,336 to Anderson discloses a phase interpolator that doubles the total number of phases available from the VCO by inserting an additional phase between two adjacent phase outputs. However, in order to double the resolution again, an additional phase interpolator would be needed. To generate a 64-phase element resolution output from a 4-phase input would require 4 such interpolators.
A paper entitled xe2x80x9cA Semi-Digital Dual Locked Loopxe2x80x9d by Stefanos Sidiropoulos and Mark Horowitz published in the November 1997 issue of IEEE Journal of Solid State Circuits teaches a phase interpolator that receives two clock signals and generates a third clock whose phase is the weighted sum of the two input phases. The weighting ratio is controlled by a digital circuit through a bus signal and its output resolution is determined by the number of control bits used. To achieve a resolution of 16 phase elements between two discrete input phases, a 4-bit control signal is required.
Since a reduction in the number of control bits can significantly reduce the complexity of the controlling circuit, and can thus reduce the semiconductor chip area used, it would be desirable to reduce the number of control bits without reducing the phase resolution. Therefore, an objective of the present invention is to teach a phase interpolator that provides a 2m phase element resolution using a control signal that contain less than m bits.
The above object has been achieved by a phase interpolator having a plurality of differential latches joined together to form a multi-stage circuit that slows down an incoming signal frequency by a factor proportional to the number of stages in the circuit. This enables the use of a faster clock as an input and makes possible the reduction in the number of control bits. For instance, a circuit with two stages will perform a divide-by-2 operation on its input. Consequently, to generate a clock frequency of 1.5625 GHz, a clock running at 3.125 GHz can be used. Since phase interpolation is performed at a doubled clock speed, the number of clock phases available will be doubled once the signal proceeds through the divide-by-2 phase interpolator. In FIG. 3, a timing diagram of a first input signal 110, a second input signal 112, and an output signal 114 of a phase interpolator of the present invention is shown. The first input signal 110 and the second input signal 112 are 90 degrees out of phase. As an example, FIG. 3 shows eight divisions between the input signals 110, 112, which imply that the overall phase element resolution is 32. However, the 32-phase element resolution in the input signals 110, 112 is transformed into a 64-phase element resolution in the output signal 114 because the clock cycle in the output is twice as long as the clock cycle in the inputs. Suppose that the desired output is a 1.5625 GHz clock with an overall 64-phase element resolution. Given a 1.5625 GHz 4-phase clock input, a conventional phase interpolator would need a 4-bit control signal to produce a stepwise resolution of 16 phase elements between any two adjacent input phases. Using the divide-by-2 phase interpolator of the present invention, a 3.125 GHz 4-phase clock could be used and only 3 control bits would be needed to generate a 1.5625 GHz clock with an overall resolution of 64 phase elements. With a divide-by-4 phase interpolator, a 6.25 GHZ 4-phase clock could be used and only 2 control bits would be needed.